Dr. Alireza Khalili
Recent developments in next generation wireless networks, like the 802.11ax and 5G standards, have introduced additional constraints to the design of radio frequency integrated circuits (RFIC). Frequency generation circuits in particular, have become some of the most difficult RFIC blocks to design as the system performance requirements have significantly shrunk the design trade-off space. Furthermore, as the race to increase the battery life and reduce RFIC costs continues, some traditional architectures have become ineffective, hence demanding new architectures and a better methodology. As a result, several new phase locked loop (PLL) and high-precision reference generator architectures have been invented and have become ubiquitous in many RF consumer electronics products. In this talk, we will discuss state of the art techniques to achieve such stringent requirements while maintaining a low cost and low power profile.
Alireza Khalili received his B.S. degree from the Sharif University of Technology, Tehran, Iran, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford CA in 2001 and 2006, respectively. Since 2006, he has been collaborating with several research institutes and companies on state-of-the-art multidisciplinary research projects in microelectronic systems and circuits. Dr. Khalili was a recipient of the Stanford Graduate Fellowship award from 1999 to 2003. He was the Gold medal winner of the National Physics Competition and the 26th International Physics Olympiad in Canberra, Australia. His research interests include novel Radio Frequency and mixed signal integrated circuits.