Mina Tahmasbi Arashloo
Post-doctoral Researcher at Cornell University
Over the past decade, network link speeds have increased rapidly, from 10Gbps to 100Gbps, and with 400Gbps Ethernet on the horizon. However, with Moore’s law slowing down and the end of Dennard scaling, CPU processing speeds and capacity have not increased as fast, making it increasingly difficult for software network stacks at the end-hosts to keep up with line rate. As such, the networking community has been exploring how to offload all or part of the processing in the network stack, which have traditionally run on general-purpose CPUs, to domain-specific hardware accelerators. These accelerators are often co-located with the network interface card (NIC) to take advantage of its strategic location between the end-host and the rest of the network, turning the regular NICs into much more advanced NICs, or “SmartNICs”. In this talk, I will give an introduction to SmartNICs and their use cases in high-speed networks and discuss a specific use case of offloading transport-layer algorithms to FPGA-based SmartNICs.